With current emphasis on increased circuit density and decreased integrated circuit package footprints, process engineers attempt to design increasingly smaller and more dense integrated circuit packages. A current outgrowth of this emphasis is the chip scale package. Typically, a chip scale package has an overall package dimension that is relatively close to that of the integrated circuit die, or chip, that is enclosed within the package. Generally, chip scale packages are manufactured either using individual chips that have been singulated from a wafer, or in wafer form and then the individual chip scale packages are singulated from the wafer. The latter type of chip scale package is referred to as a wafer level chip scale package.
One example of a wafer level chip scale package is a surface mount die, such as a flip chip package. Surface mount dice typically have input/output contacts, such as solder bumps, that are located on the active side of the die.
FIG. 1A is a diagrammatic side view of a conventional flip chip package. Typically, the flip chip package 100 includes a die 102 having a plurality of conventionally fabricated integrated circuit structures, such as transistors, etc. (not shown). The top surface of the die 102 includes contact pads 104 which provide for conductive interconnection to the integrated circuit structures of the die 102. Contact bumps 106, such as solder bumps, are conventionally formed on the contact pads 104 to allow for interconnection of the package to other substrates. The bottom surface of the die 102 is conventionally left bare. Typically, a plurality of flip chip packages 100 are formed on the surface of an integrated circuit wafer (not shown). After fabrication of the flip chip packages, the wafer is singulated into individual flip chip packages 100, for example, by laser cutting or sawing. The individual flip chips may then be inverted and attached to a substrate, such as a printed circuit board.
In attaching the flip chip to the substrate, the contact bumps are typically aligned and electrically coupled to an associated board contact of the substrate, for example, by a reflow process, which forms a solder joint. In this way, a high density of input/output pads are provided within a small package footprint as the contact pads are over the die itself. A disadvantage of this design is that stresses introduced on the contact bumps may damage the flip chip package.
FIG. 1B is a diagrammatic side view of a conventional flip chip package attached to a substrate. Typically, the die 102 of the flip chip package 100 and the substrate 110 are formed from different materials that may have substantially different coefficients of thermal expansion. When the flip chip contact bumps 106 are attached to the contact pads 108 of the substrate 110 and power is applied, the resultant heat dissipates in the die 102 and the substrate 110 causing each to expand and contract in different amounts. This causes the contact bumps 106, which are on the contact pads 104 of the die 102, to move relative to the contact pads 108 of the substrate 110.
As the solder joint in this design is a relatively rigid joint structure, the relative movement can deform and stress the contact bumps 106 and may ultimately result in damage to the flip chip package 100, for example, solder joint fatigue. Further, the stresses on the contact bumps 106 may push the contact bumps 106 into the underlying layers that form the die 102 and cause craters within the die 102. Additionally, the stresses may cause the contact bumps 106 to tear open.
To mitigate the effects of the stresses, an underfill layer 112 is typically injected between the substrate 110 and the flip chip package 100 and around the contact bumps 106 of the flip chip package 100. The underfill layer 112 helps to reduce the stress effects of the differential thermal expansion between the die 102 and the substrate 110 and to improve the reliability of the package. However, the addition of the underfill layer 112 results in an extra processing step and increased associated costs, thus impacting overall production costs and production yield. Additionally, as the contact bumps 106 and underfill layer 112 are rigidly attached to the die 102, the package 100 still retains some stress-related problems which can be transferred to and damage the die 102.
Further, the design of the package 100 restrains both the arrangement of the contact bumps 106 and the arrangement of the contact pads 108 of a substrate to the arrangement of the contact pads 104 on the die 102. Thus, this design tends to limit the packaging to use with smaller die sizes/pin counts, for example, 3×3 mm size/28–40 leads.
In an attempt to relieve the contact restraints, another design, further described in U.S. Pat. No. 5,990,546 to Igarashi et al., utilizes an auxiliary wiring plate over the die on which external contacts for connecting to a substrate can be formed and surrounds the die and the space between the die and the auxiliary wiring plate with a resin. The auxiliary wiring plate may have contacts differently located on each side to provide more flexibility in locating the external contacts. This package, however, is not manufactured at the wafer level, and instead, the package is formed using individual chips singulated from a wafer.
FIG. 2 is a diagrammatic side view of an example of a semiconductor package 200 utilizing an auxiliary wiring plate with external contacts formed on the wiring plate and resin interposed between the wiring plate and the die. The semiconductor package 200 includes an integrated circuit die 202, an auxiliary wiring plate 204, and a resin layer 206 sealing the space between the die 202 and the auxiliary wiring plate 204. The die 202 typically includes a plurality of conventionally fabricated integrated circuit structures. The top surface of the die 202 includes contacts 208, which provide interconnection to the integrated circuit structures of the die 202. The auxiliary wiring plate 204 includes an inner electrode 210 coupled with the contacts 208 of the die 202, an outer electrode 212 located at a different position from the back position of the inner electrode 210, a routing conductor 214 extended between both electrodes 210 and 212, and insulating layers 216 and 218 formed on both surfaces of the routing conductor 214.
According to one method, the package 200 can be made using the tape-automated bonding technique in which the auxiliary wiring plate 204, including the inner and outer electrodes 210 and 212 with routing conductors 214, is initially fabricated. Then the contacts 208 of the die 202 are connected to the inner electrode 210 and the insulating support film 216 and the die 202 are sealed with resin to form the package 200. The film carrier tape is then punched out to define the periphery of the die 202.
Another design, further described in U.S. Pat. No. 6,020,220 to Gilleo et al., attempts to mitigate the stresses received at the die by utilizing a less rigid underfill layer and a flexible wiring layer over the underfill layer on which external contacts for connecting to a substrate can be formed. The compliance in the interposer layer and in the conductive polymer are utilized to permit relative movement of the connections on the dielectric substrate wiring layer to the die contacts to mitigate the stress caused by differential thermal expansion. Again, however, this package is not manufactured at the wafer level, and instead, the package is formed using individual chips singulated from a wafer.
FIG. 3 is a diagrammatic side view of an example of a semiconductor package 300 utilizing a compliant interposer layer and flexible wiring layer. The semiconductor package 300 includes a die 302, a compliant interposer layer 304, and a dielectric substrate wiring layer 306. The die 302 typically includes a plurality of conventionally fabricated integrated circuit structures. The top surface of the die 302 includes contacts 308, which provide interconnection to the integrated circuit structures of the die 302. The compliant interposer layer 304 has conductive columns 310 that are aligned with and provide conductive interconnection to the contacts 308. The dielectric substrate wiring layer 306 is typically a flexible, film circuit element. The dielectric substrate wiring layer 306 has a bottom surface which includes bond pads 312 interconnected to bond pads 314 on the top surface on which conductive contacts 316, such as solder balls, may be formed to allow connection to another substrate, such as a printed circuit board. The dielectric substrate wiring layer 306 is attached to the compliant interposer layer 304 such that the bond pads 312 are aligned and attached with the corresponding conductive column 310. According to one method, the package is made on the dielectric substrate wiring layer 306 and then attached to the die 302 using heat and pressure.
Consequently, there is a need for a wafer level fabricated chip scale integrated circuit package design that can further decouple the stresses between the package and other substrates to which it is attached, and can provide flexibility in the arrangement of the package contacts to other substrates.